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| PRELIMINARY DATA SHEET PD72870,72871 IEEE1394 1-CHIP OHCI HOST CONTROLLER MOS INTEGRATED CIRCUIT The PD72870, 72871 are the LSIs which integrated OHCI-Link and PHY function into a single chip. The PD72870, 72871 comply with the P1394a draft 2.0 specifications and the OpenHCI IEEE1394 1.0 and work up to 400 Mbps. These make design so compact for PC and PC card application. FEATURES * Compliant with Link Layer Services as defined in 1394 Open Host Controller Interface specification release 1.0 * Compliant with Physical Layer Services as defined in P1394a draft 2.0 (Data Rate 100/200/400 Mbps) 3-port : PD72870 1-port : PD72871 * Compliant with protocol enhancement as defined in P1394a draft 2.0 * Modular 32-bit host interface compliant to PCI Specification release 2.1 * Support PCI-Bus Power Management Interface Specification release 1.0 * Modular 32-bit host interface compliant to Card Bus Specification * Cycle Master and Isochronous Resource Manager capable 5 * Built-in FIFOs for isochronous transmit (1024 bytes), asynchronous transmit (1024 bytes), and receive (2048 bytes) * 32-bit CRC generation and checking for receive/transmit packets * 4 isochronous transmit DMAs and 4 isochronous receive DMAs supported * 32-bit DMA channels for physical memory read/write * Clock generation by 24.576 MHz X'tal * Internal control and operational registers direct-mapped to PCI configuration space * 2-wire Serial EEPROMTM interface supported * Separate power supply Link and PHY ORDERING INFORMATION Part number Package 160-pin plastic LQFP (Fine pitch) (24 x 24 mm) 192-pin Plastic FBGA (14 x 14 mm) 160-pin plastic LQFP (Fine pitch) (24 x 24 mm) 192-pin Plastic FBGA (14 x 14 mm) PD72870GM-8ED PD72870F1-FA2 PD72871GM-8ED PD72871 F1-FA2 The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S13925EJ2V0DS00 (2nd edition) Date Published September 1999 NS CP(K) Printed in Japan The mark 5 shows major revised points. 1999 PD72870,72871 BLOCK DIAGRAMS Top Block Diagram Serial ROM Interface PCI Bus/ Cardbus Link PHY Cable Interface PHY Signal 2 Preliminary Data Sheet S13925EJ2V0DS00 PD72870,72871 PHY Block Diagram PHY Control Signal (CMC,PC0-PC2) Cable Port1 Arbitration and Control State Machine Logic PHY/Link Interface Link Interface I/O Cable Port2 Cable Interface Cable Port3 Receive Data Decoder and Retimer Voltage and Current Generator PHY Signal Transmit Data Encoder Cable Power Status Crystal Oscillator PLL System and Transmit Clock Generator Remark Cable Port: Preliminary Data Sheet S13925EJ2V0DS00 3 PD72870,72871 Link Block Diagram Serial ROM Interface PCI Bus / Cardbus Interface PCI Controller Interface (Master, Parity Check & Generator) Byte Buf Swap PCI-DMA IOREG CSR (CIS) PFCOMM Byte Swap ATF Byte Swap ITF PCICFG ATDMA PAU GRSU ITCF Byte RF Swap Link Layer Core OPCIBUS_ARB GRQU ITDMA IRDMA0IRDMA3 SFIDU RCF IOREG ATDMA ATF CIS CSR IOREG IRDMA ITCF ITDMA ITF OPCIBUS_ARB PAU PCICFG PCIS_CNT PFCOMM RCF RF SFIDU : Asynchronous Transmit DMA : Asynchronous Transmit FIFO : CIS Register : Control and Status Registers : IO Registers : Isochronous Receive DMA : Isochronous Transmit Control FIFO : Isochronous Transmit DMA : Isochronous Transmit FIFO : OPCI Internal Bus Arbitration : Physical Response and Request Unit : PCI Configuration Registers : PHY Control Isochronous Control : Pre Fetch Command FIFO : Receive Control FIFO : Receive FIFO : Self-ID DMA 4 Preliminary Data Sheet S13925EJ2V0DS00 PHY/Link Interface OPCI Internal Bus PCIS Bus (PCI Slave Bus) PCIS_CNT PD72870,72871 5 PIN CONFIGURATION * 160-pin plastic LQFP (Fine pitch) (24 x 24 mm) PD72870GM-8ED Top View DGND IC(L) IC(L) CARD_ON CIS_ON GROM_EN GROM_SCL GROM_SDA DGND L_VDD DGND P_DVDD P_AVDD P_AVDD P_AVDD AGND AGND AGND AGND AGND TpA0p TpA0n TpB0p TpB0n TpA1p TpA1n TpB1p TpB1n TpA2p TpA2n TpB2p TpB2n TpBias0 TpBias1 TpBias2 P_AVDD AGND CPS RI1 RI0 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 L_VDD CLKRUN PME INTA PRST PCLK GNT REQ DGND PCI_VDD AD31 AD30 AD29 AD28 DGND AD27 AD26 AD25 AD24 L_VDD DGND CBE3 IDSEL AD23 AD22 AD21 AD20 DGND AD19 AD18 PCI_VDD AD17 AD16 DGND CBE2 FRAME IRDY TRDY DEVSEL L_VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P_AVDD AGND XO XI P_AVDD FIL0 FIL1 AGND AGND P_AVDD P_RESETB DGND P_DVDD P_AVDD SUS_RESM PORTDIS DGND P_DVDD IC(L) IC(L) IC(H) IC(H) DGND P_DVDD CMC PC2 PC1 PC0 IC(N) IC(L) DGND IC(L) IC(N) IC(N) IC(N) DGND IC(N) IC(N) IC(N) L_VDD DGND STOP PERR SERR PAR L_VDD CBE1 DGND AD15 AD14 PCI_VDD AD13 AD12 DGND AD11 AD10 AD9 AD8 L_VDD CBE0 AD7 AD6 AD5 AD4 DGND AD3 AD2 AD1 AD0 PCI_VDD DGND L_VDD PIN_EN IC(N) IC(H) IC(N) IC(N) IC(N) IC(N) DGND Preliminary Data Sheet S13925EJ2V0DS00 5 PD72870,72871 * 160-pin plastic LQFP (Fine pitch) (24 x 24 mm) PD72871GM-8ED Top View DGND IC(L) IC(L) CARD_ON CIS_ON GROM_EN GROM_SCL GROM_SDA DGND L_VDD DGND P_DVDD P_AVDD P_AVDD P_AVDD AGND AGND AGND AGND AGND TpA0p TpA0n TpB0p TpB0n NC NC NC NC NC NC NC NC TpBias0 NC NC P_AVDD AGND CPS RI1 RI0 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 L_VDD CLKRUN PME INTA PRST PCLK GNT REQ DGND PCI_VDD AD31 AD30 AD29 AD28 DGND AD27 AD26 AD25 AD24 L_VDD DGND CBE3 IDSEL AD23 AD22 AD21 AD20 DGND AD19 AD18 PCI_VDD AD17 AD16 DGND CBE2 FRAME IRDY TRDY DEVSEL L_VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P_AVDD AGND XO XI P_AVDD FIL0 FIL1 AGND AGND P_AVDD P_RESETB DGND P_DVDD P_AVDD SUS_RESM PORTDIS DGND P_DVDD IC(L) IC(L) IC(H) IC(H) DGND P_DVDD CMC PC2 PC1 PC0 IC(N) IC(L) DGND IC(L) IC(N) IC(N) IC(N) DGND IC(N) IC(N) IC(N) L_VDD 6 DGND STOP PERR SERR PAR L_VDD CBE1 DGND AD15 AD14 PCI_VDD AD13 AD12 DGND AD11 AD10 AD9 AD8 L_VDD CBE0 AD7 AD6 AD5 AD4 DGND AD3 AD2 AD1 AD0 PCI_VDD DGND L_VDD PIN_EN IC(N) IC(H) IC(N) IC(N) IC(N) IC(N) DGND Preliminary Data Sheet S13925EJ2V0DS00 PD72870,72871 * 192-pin Plastic FBGA (14 x 14 mm) PD72870 F1-FA2 PD72871 F1-FA2 Bottom View 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 TRPNMLKJHGFEDCBA Top View ABCDEFGHJ KLMNPRT Index mark Remark : Pin connected on the FPBGA board. Preliminary Data Sheet S13925EJ2V0DS00 7 8 Preliminary Data Sheet S13925EJ2V0DS00 PD72870 F1-FA2 A 16 RI0 B RI1 C AGND P_AV D XO E FIL0 F G Top View H PORTDIS J IC(L) K CMC L PC1 M IC(L) N IC(N) P IC(N) R L_V DD T DGND P_RESETB P_AVDD P_AV 15 CPS AGND DD XI P_AV FIL1 DD SUS_RESM P_DV DGND P_DV IC(H) PC2 P_DV PC0 DGND IC(N) IC(N) IC(N) IC(N) 14 TpBias2 TpBias1 TpBias0 DD AGND DGND DD DD IC(H) DD IC(N) P_DV IC(L) DGND L_V IC(N) IC(N) IC(N) 13 TpB2n TpB2p AGND P_AV DD AGND DGND P_DV DD IC(L) DGND P_DV DD DD IC(N) DD PIN_EN IC(N) IC(H) 12 TpA2n TpA2p AGND P_AV DD PCI_V DD DGND AD1 AD0 11 TpB1n TpB1p AGND P_AVDD PCI_V DD DGND AD3 AD2 10 TpA1n TpA1p AGND AGND L_V DD DGND AD5 AD4 9 TpB0n TpB0p AGND AGND L_V DD CBE0 AD7 AD6 8 TpA0n TpA0p AGND AGND DGND DGND AD9 AD8 7 AGND AGND P_AV AGND P_AV AGND P_AV DGND PCI_V DGND PCI_V AD11 AD10 6 AGND P_DV DD DD DD DD DD AD13 AD12 5 DD DGND L_V DD DGND L_V L_V L_V L_V DD DGND AD15 AD14 PD72870,72871 4 GROM_SDA GROM_SCL GROM_EN IC(L) DGND PCI_V DGND PCI_V DGND DGND DD DD DD DGND DGND PCI_V DGND L_V PAR CBE1 3 CIS_ON L_V CARD_ON IC(L) DGND DD DD DGND DGND DGND DGND DGND DGND DD DD PERR SERR 2 DD PME PRST GNT AD31 AD29 AD27 AD25 CBE3 AD23 AD21 AD19 AD17 CBE2 IRDY STOP 1 CLKRUN INTA PCLK REQ AD30 AD28 AD26 AD24 IDSEL AD22 AD20 AD18 AD16 FRAME TRDY DEVSEL PD72871 F1-FA2 A 16 RI0 B RI1 C AGND P_AV D XO E FIL0 F G Top View H PORTDIS J IC(L) K CMC L PC1 M IC(L) N IC(N) P IC(N) R L_V DD T DGND P_RESETB P_AVDD P_AV 15 CPS AGND DD XI P_AV FIL1 DD SUS_RESM P_DV DGND P_DV IC(H) PC2 P_DV PC0 DGND IC(N) IC(N) IC(N) IC(N) 14 NC NC TPBias0 DD AGND DGND DD DD IC(H) DD IC(N) P_DV IC(L) DGND L_V IC(N) IC(N) IC(N) 13 NC NC AGND P_AV DD AGND DGND P_DV DD IC(L) DGND P_DV DD DD IC(N) DD PIN_EN IC(N) IC(H) 12 Preliminary Data Sheet S13925EJ2V0DS00 NC NC AGND P_AV DD PCI_V DD DGND AD1 AD0 11 NC NC AGND P_AVDD PCI_V DD DGND AD3 AD2 10 NC NC AGND AGND L_V DD DGND AD5 AD4 9 TpB0n TpB0p AGND AGND L_V DD CBE0 AD7 AD6 8 TpA0n TpA0p AGND AGND DGND DGND AD9 AD8 7 AGND AGND P_AV AGND P_AV AGND P_AV DGND PCI_V DGND PCI_V AD11 AD10 6 AGND P_DV DD DD DD DD DD AD13 AD12 5 DD DGND L_V DD DGND L_V L_V L_V L_V DD DGND AD15 AD14 PD72870,72871 4 GROM_SDA GROM_SCL GROM_EN IC(L) DGND PCI_V DGND PCI_V DGND DGND DD DD DD DGND DGND PCI_V DGND L_V PAR CBE1 3 CIS_ON L_V CARD_ON IC(L) DGND DD DD DGND DGND DGND DGND DGND DGND DD DD PERR SERR 2 DD PME PRST GNT AD31 AD29 AD27 AD25 CBE3 AD23 AD21 AD19 AD17 CBE2 IRDY STOP 1 CLKRUN INTA PCLK REQ AD30 AD28 AD26 AD24 IDSEL AD22 AD20 AD18 AD16 FRAME TRDY DEVSEL 9 PD72870,72871 5 PIN NAME AD0-AD31 AGND : PCI Multiplexed Address and Data : Analog GND PME PORTDIS PRST P_AVDD P_DVDD REQ RI0 RI1 SERR STOP Tp0n TpA0p TpA1n TpA1p TpA2n TpA2p TpB0n TpB0p TpB1n TpB1p TpB2n TpB2p TpBias0 TpBias1 TpBias2 TRDY XI XO : PME Output : Port Disable : Reset : PHY Analog VDD : PHY Digital VDD : Bus_master Request : Resistor0 for Reference Current Setting : Resistor1 for Reference Current Setting : System Error : PCI Stop : Port-1 Twisted Pair A Negative Input/Output : Port-1 Twisted Pair A Positive Input/Output : Port-2 Twisted Pair A Negative Input/Output : Port-2 Twisted Pair A Positive Input/Output : Port-3 Twisted Pair A Negative Input/Output : Port-3 Twisted Pair A Positive Input/Output : Port-1 Twisted Pair B Negative Input/Output : Port-1 Twisted Pair B Positive Input/Output : Port-2 Twisted Pair B Negative Input/Output : Port-2 Twisted Pair B Positive Input/Output : Port-3 Twisted Pair B Negative Input/Output : Port-3 Twisted Pair B Positive Input/Output : Port-1 Twisted Pair Bias Voltage Output : Port-2 Twisted Pair Bias Voltage Output : Port-3 Twisted Pair Bias Voltage Output : Target Ready : X'tal XI : X'tal XO CARD_ON : PCI/Card Select CBE0-CBE3 : Command/Byte Enables CIS_ON CLKRUN CMC CPS DEVSEL DGND FIL0 FIL1 FRAME GNT : CIS Register ON : PCICLK Running : Configuration Manager Capable : Cable Power Status Input : Device Select : Digital GND : APLL Filter GND : APLL Filter Terminal : Cycle Frame : Bus_master Grant P_RESETB : PHY Power on Reset Input SUS_RESM : Suspend/Resume Function Select GROM_EN : Serial EEPROM Enable GROM_SCL : Serial EEPROM Clock Output GROM_SDA : Serial EEPROM Data Input / Output IC(H) IC(L) IC(N) IDSEL INTA IRDY L_VDD PAR PC0-PC2 PCI_VDD PCLK PERR PIN_EN : Internally Connected (High Clamped) : Internally Connected (Low Clamped) : Internally Connected (Open) : ID Select : Interrupt : Initiator Ready : VDD for Link Digital Core and Link I/Os : Parity : Power Class Input : VDD for PCI I/Os : PCI Clock : Parity Error : Pin Enable Input 10 Preliminary Data Sheet S13925EJ2V0DS00 PD72870,72871 CONTENTS 1. PIN FUNCTIONS ................................................................................................................................... 13 1.1 PCI/Cardbus Interface Signals: (52 pins)..................................................................................... 13 1.2 Cable Interface Signals: (15 pins) ................................................................................................ 14 1.3 PHY Signals: (9 pins)..................................................................................................................... 15 1.4 PHY Control Signals: (5 pins) ....................................................................................................... 15 1.5 PCI/Cardbus Select Signals: (2 pins) ........................................................................................... 16 1.6 Serial ROM Interface Signals: (3 pins) ......................................................................................... 16 1.7 Miscellaneous Signals: (1 pin)...................................................................................................... 16 1.8 IC: ( 21 pins) ................................................................................................................................... 17 1.9 VDD ................................................................................................................................................... 17 1.10 GND ............................................................................................................................................... 17 2. PHY REGISTERS .................................................................................................................................. 18 2.1 Complete Structure for PHY Registers ........................................................................................ 18 2.2 Port Status Page (Page 000) ......................................................................................................... 21 2.3 Vendor ID Page (Page 001) ........................................................................................................... 22 3. CONFIGURATION REGISTERS........................................................................................................... 23 3.1 PCI Bus Mode Configuration Register ( CARD_ON=Low ) ........................................................ 23 3.1.1 Offset_00 3.1.2 Offset_02 3.1.3 Offset_04 3.1.4 Offset_06 3.1.5 Offset_08 3.1.6 Offset_09 3.1.7 Offset_0C 3.1.8 Offset_0D 3.1.9 Offset_0E 3.1.11 Offset_10 3.1.12 Offset_20 3.1.13 Offset_22 3.1.14 Offset_30 3.1.15 Offset_34 3.1.16 Offset_3C 3.1.17 Offset_3D 3.1.18 Offset_3E 3.1.19 Offset_3F 3.1.20 Offset_40 3.1.21 Offset_60 3.1.22 Offset_62 3.1.23 Offset_64 3.2.1 Offset_14/18 3.2.2 Offset_28 3.2.3 Offset_80 Vendor ID Register............................................................................................................ 24 DeviceID Register ............................................................................................................. 24 Command Register ........................................................................................................... 24 Status Register.................................................................................................................. 25 Revision ID Register.......................................................................................................... 26 Class Code Register ......................................................................................................... 26 Cache Line Size Register ................................................................................................. 26 Latency Timer Register..................................................................................................... 26 Header Type Register....................................................................................................... 26 Base Address 0 Register................................................................................................. 27 Subsystem Vendor ID Register ....................................................................................... 27 Subsystem ID Register.................................................................................................... 27 Expansion Rom Base Address Register ......................................................................... 27 Cap_Ptr Register............................................................................................................. 27 Interrupt Line Register .................................................................................................... 28 Interrupt Pin Register...................................................................................................... 28 Min_Grant Register......................................................................................................... 28 Max Lat Register ............................................................................................................. 28 PCI_OHCI_Control Register ........................................................................................... 28 Cap_ID & Next_Item_Ptr Register .................................................................................. 29 Power Management Capabilities Register ...................................................................... 29 Power Management Control/Status Register .................................................................. 30 Base_Address_1/2 Register (CardBus Status Registers)............................................ 32 3.1.10 Offset_0F BIST Register................................................................................................................... 26 3.2 CardBus Mode Configuration Register ( CARD_ON=High ) ...................................................... 31 Cardbus CIS Pointer ......................................................................................................... 33 CIS Area............................................................................................................................ 33 Preliminary Data Sheet S13925EJ2V0DS00 11 PD72870,72871 4. PHY FUNCTION .................................................................................................................................... 34 4.1 Cable Interface ............................................................................................................................... 34 4.1.1 Connections .......................................................................................................................................... 34 4.1.2 Cable Interface Circuit .......................................................................................................................... 35 4.1.3 CPS....................................................................................................................................................... 35 4.1.4 Unused Ports ........................................................................................................................................ 35 4.2 PLL and Crystal Oscillation Circuit.............................................................................................. 35 4.2.1 Crystal Oscillation Circuit...................................................................................................................... 35 4.2.2 PLL ....................................................................................................................................................... 35 4.3 PC0-PC2, CMC................................................................................................................................ 35 4.4 P_RESETB ...................................................................................................................................... 35 4.5 RI0, RI1 ............................................................................................................................................ 35 5. SERIAL ROM INTERFACE .................................................................................................................. 36 5.1 Serial EEPROM Register ............................................................................................................... 36 5.2 Serial EEPROM Register Description .......................................................................................... 36 5.3 Load Control................................................................................................................................... 40 6. ELECTRICAL SPECIFICATIONS ......................................................................................................... 41 7. APPLICATION CIRCUIT EXAMPLE.................................................................................................... 44 8. PACKAGE DRAWINGS ........................................................................................................................ 45 12 Preliminary Data Sheet S13925EJ2V0DS00 PD72870,72871 1. PIN FUNCTIONS 1.1 PCI/Cardbus Interface Signals: (52 pins) (1/2) Name I/O Pin No. LQFP PAR I/O 45 FPBGA R4 PCI/Cardbus IOL Volts(V) Function 5/3.3 Parity is even parity across AD0-AD31 and CBE0-CBE3. It is an input when AD0-AD31 is an input; it is an output when AD0AD31 is an output. AD0-AD31 I/O 11-14, 16-19, 24-27, 29,30,32, 33,49,50, 52,53, 55-58, 61-64, 66-69 E1,E2, F1,F2, G1,G2, H1,H2, K1,K2, L1,L2, M1,M2, N1,N2, R5-R12, T5-T12 PCI/Cardbus 5/3.3 PCI Multiplexed Address and Data CBE0-CBE3 I 22,35,47, 60 J2,P2,P9, T4 P1 - 5/3.3 Command/Byte Enables are multiplexed Bus Commands & Byte enables. FRAME I/O 36 PCI/Cardbus 5/3.3 Cycle Frame is asserted by the initiator to indicate the cycle beginning and is kept asserted during the burst cycle. 5 TRDY I/O 38 R1 PCI/Cardbus If Cardbus mode (CARD_ON = 1), this pin is should be pulled up to VDD. 5/3.3 Target Ready indicates that the current data phase of the transaction is ready to be completed. IRDY I/O 37 R2 PCI/Cardbus 5/3.3 Initiator Ready indicates that the current bus master is ready to complete the current data phase. During a write, its assertion indicates that the initiator is driving valid data onto the data bus. During a read, its assertion indicates that the initiator is ready to accept data from the currently-addressed target. REQ O 8 D1 PCI/Cardbus 5/3.3 Bus_master Request indicates to the bus arbiter that this device wants to become a bus master. GNT I 7 D2 - 5/3.3 Bus_master Grant indicates to this device that access to the bus has been granted. IDSEL I 23 J1 - 5/3.3 ID Select when actively driven, indicates that the IUHC is chipselected for configuration read/write transaction during the phase of device initialization. 5 DEVSEL I/O 39 T1 PCI/Cardbus If Cardbus mode (CARD_ON = 1), this pin is should be pulled up to VDD. 5/3.3 Device Select when actively driven, indicates that the driving device has decoded its address as the target of the current access. STOP I/O 42 T2 PCI/Cardbus 5/3.3 PCI Stop when actively driven, indicates that the target is requesting the current bus master to stop the transaction. Preliminary Data Sheet S13925EJ2V0DS00 13 PD72870,72871 (2/2) Name I/O Pin No. LQFP PME O 3 FPBGA B2 PCI/Cardbus IOL Volts(V) Function 5/3.3 PME Output for power management enable. 5 Caution The PME pin is not an N-channel open drain structure pin. Therefore, when using S3, S4, S5 state in ACPI, a circuit that can separate between the power supply and the PME pin externally is needed. ACPI: Advanced Configuration and Power Interface. Please refer to ACPI Specification. CLKRUN I/O 2 A1 PCI/Cardbus 5/3.3 PCICLK Running as input, to determine the status of PCLK; as output, to request starting or speeding up clock. INTA PERR O I/O 4 43 B1 R3 PCI/Cardbus PCI/Cardbus 5/3.3 5/3.3 Interrupt the PCI interrupt request A. Parity Error is used for reporting data parity errors during all PCI transactions, except a Special Cycle. It is an output when AD0-AD31 and PAR are both inputs. It is an input when AD0AD31 and PAR are both outputs. SERR O 44 T3 PCI/Cardbus 5/3.3 System Error is used for reporting address parity errors, data parity errors during the Special Cycle, or any other system error where the effect can be catastrophic. When reporting address parity errors, it is an output. PRST PCLK I I 5 6 C2 C1 - 5/3.3 5/3.3 Reset PCI reset PCI Clock 33 MHz systembus clock. 1.2 Cable Interface Signals: (15 pins) (1/2) Name I/O Pin No. LQFP TpA0p TpA0n TpB0p TpB0n TpA1p Note 1 IOL Volts(V) Function Port-1 Twisted Pair A Positive Input/Output Note 2 Port-1 Twisted Pair A Negative Input/Output Note 2 Port-1 Twisted Pair B Positive Input/Output Note 2 Port-1 Twisted Pair B Negative Input/Output Note 2 Port-2 Twisted Pair A Positive Input/Output Note 2 Port-2 Twisted Pair A Negative Input/Output Note 2 Port-2 Twisted Pair B Positive Input/Output Note 2 Port-2 Twisted Pair B Negative Input/Output Note 2 Port-3 Twisted Pair A Positive Input/Output Note 2 Port-3 Twisted Pair A Negative Input/Output Note 2 Port-3 Twisted Pair B Positive Input/Output Note 2 Port-3 Twisted Pair B Negative Input/Output Note 2 FPBGA B8 A8 B9 A9 B10 A10 B11 A11 B12 A12 B13 A13 - I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 140 139 138 137 136 135 134 133 132 131 130 129 TpA1n Note 1 TpB1p Note 1 TpB1n Note 1 TpA2p Note 1 TpA2n Note 1 TpB2p Note 1 TpB2n Note 1 Note 1. PD72870 only. In PD72871, it is open. 2. If unused port, please refer to 4.1.4 Unused Port. 14 Preliminary Data Sheet S13925EJ2V0DS00 PD72870,72871 (2/2) Name PORTDIS I/O I 105 Pin No. LQFP FPBGA H16 Port Disable SUS_RESM = "1" This selected state will be loaded to Disabled bit which allocated PHY register Port Status Page. 1:Disable At this time, all ports will be disabled (PD72870: 3ports, IOL Volts(V) Function PD72871: 1port). SUS_RESM="0" PORTDIS has no effect. SUS_RESM I 106 G15 Suspend/Resume Function Select 1 : Suspend/Resume On (P1394a draft 2.0 compliant) 0 : Suspend/Resume Off (P1394a draft 1.3 compliant) CPS I 123 A15 Cable Power Status Input Note Note Please refer to 4.1.3 CPS. 1.3 PHY Signals: (9 pins) Name I/O Pin No. LQFP TpBias0 TpBias1 Note1 TpBias2 Note1 RI0 RI1 O O O I O 128 127 126 121 122 114 115 117 118 FPBGA C14 B14 A14 A16 B16 E15 E16 D15 D16 Port-1 Twisted Pair Bias Voltage Output Note 2 Port-2 Twisted Pair Bias Voltage Output Note 2 Port-3 Twisted Pair Bias Voltage Output Note 2 Resistor0 for Reference Current Setting Note 3 Resistor1 for Reference Current Setting Note 3 APLL Filter Terminal (No need to assemble) APLL Filter GND (No need to assemble) X'tal XI X'tal XO IOL Volts(V) Function 5 5 FIL1 FIL0 XI XO Note 1. PD72870 only. In PD72871, it is open. 2. If unused port, please refer to 4.1.4 Unused Port. 3. Please refer to 4.5 RI0, RI1. 1.4 PHY Control Signals: (5 pins) Name I/O Pin No. LQFP PC0-PC2 I 93-95 FPBGA K15,L15, L16 CMC P_RESETB I I 96 110 K16 F16 3.3 Configuration Manager Capable Note 1 PHY Power on Reset Input Note 2 3.3 Power Class Input Note 1 IOL Volts(V) Function Note 1. Please refer to 4.3 PC0-PC2, CMC. 2. Please refer to 4.4 P_RESETB. Preliminary Data Sheet S13925EJ2V0DS00 15 PD72870,72871 1.5 PCI/Cardbus Select Signals: (2 pins) Name I/O Pin No. LQFP CARD_ON CIS_ON I I 157 156 FPBGA B3 A3 3.3 3.3 PCI/Card Select (1:Cardbus, 0:PCI bus) CIS Register ON CARD_ON 0 0 1 CIS_ON 1 0 X CIS off on on PME PME CSTSCHG CSTSCHG IOL Volts(V) Function 1.6 Serial ROM Interface Signals: (3 pins) Name I/O Pin No. LQFP GROM_SDA GROM_SCL GROM_EN I/O O I 153 154 155 FPBGA A4 B4 C4 6mA 6mA 3.3 3.3 3.3 Serial EEPROM Data Input / Output Serial EEPROM Clock Output Serial EEPROM Enable (`high': GUID Load enabled, `low': GUID Load disabled) IOL Volts(V) Function 1.7 Miscellaneous Signals: (1 pin) Name I/O Pin No. LQFP PIN_EN I 73 FPBGA P13 5/3.3 Pin Enable Input (High clamped) IOL Volts(V) Function 16 Preliminary Data Sheet S13925EJ2V0DS00 PD72870,72871 5 1.8 IC: ( 21 pins) Name I/O LQFP IC(H) IC(L) I I 75,99,100 89,91,101,102,158, 159 IC(N) 74,76-79,82-84, 86-88,92 Pin No. FPBGA J14,J15,T13 C3,D4,H13,J16, M14,M16 L14,M13,N15,N16, P14-P16,R13-R15, T14,T15 Internally Connected (Open) Internally Connected (High clamped) Internally Connected (Low clamped) IOL Volts(V) Function 1.9 VDD Name I/O LQFP PCI_VDD 10,31,51,70 Pin No. FPBGA E3,F3,N3,N6, N11,N12,P6 L_VDD 1,20,40,46,59,72,81, 151 P_DVDD 97,103,108,149 A2,C5,J4,K4,L4,N5, N9,N10,N13,P3,R16 A5,G13,G14,H14,K13, K14,L13 P_AVDD 111 107,116 120,125 146-148 F15 D14,G16 C15,D11-D13 B6,C6,D6 3.3 3.3 3.3 3.3 PHY PLL VDD PHY PLL,OSC VDD PHY Bias VDD PHY Port VDD 3.3 PHY digital VDD 3.3 VDD for Link digital Core and Link I/Os 5/3.3 VDD for PCI I/Os IOL Volts(V) Function 1.10 GND Name I/O LQFP DGND 9,15,21,28,34,41,48, Pin No. FPBGA B5,D3,D5,E4,F4,F13, Digital GND IOL Volts(V) Function 54,65,71,80,85,90,98, F14,G3,G4,H3,H4, 104,109,150,152,160 H15,J3,J13,K3,L3, M3,M4,M15,N4,N7, N8,N14,P4,P5,P7,P8, P10-P12,T16 AGND 112 113 119,124 141 142 143,144,145 E13 E14 B15,C16 A7 B7 A6,C7-C13,D7-D10 PHY PLL GND PHY PLL,OSC GND PHY Bias GND PHY Common GND PHY Speed Signal GND PHY Port GND Preliminary Data Sheet S13925EJ2V0DS00 17 PD72870,72871 2. PHY REGISTERS 2.1 Complete Structure for PHY Registers Figure 2-1. Complete Structure of PHY Registers 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Page_select Link_active Resume_int RHB IBR Extended (7) Max_speed Contender ISBR Loop Reserved Reserved Jitter Pwr_fail Timeout Port_event 1 2 Physical_ID Gap_count Total_ports Delay Pwr_class Enab_accel Enab_multi 3 4 5 6 R 7 PS Reserved Reserved Register0 (page_select) Register1 (page_select) Register2 (page_select) Register3 (page_select) Register4 (page_select) Register5 (page_select) Register6 (page_select) Register7 (page_select) Port_select Table 2-1. Bit Field Description (1/3) Field Physical_ID R Size 6 1 R/W R R Reset value 000000 0 Description Physical_ID value selected from Self_ID period. If this bit is 1, the node is root. 1: Root 0: Not root PS 1 R Cable power status. 1: Cable power on 0: Cable power off RHB IBR 1 1 R/W R/W 0 0 Root Hold -off bit. If 1, becomes root at the bus reset. Initiate bus reset. Setting to 1 begins a long bus reset. Long bus reset signal duration: 166 sec. Returns to 0 at the beginning of bus reset. Gap_count 6 R/W 111111 Gap count value. It is updated by the changes of transmitting and receiving the PHY configuration packet Tx/Rx. The value is maintained after first bus reset. After the second bus reset it returns to reset value. 18 Preliminary Data Sheet S13925EJ2V0DS00 PD72870,72871 Table 2-1. Bit Field Description (2/3) Field Extended Total_ports Size 3 4 R/W R R Reset value 111 0011 or 0001 Max_speed 3 R 010 Description Shows the extended register map. Supported port number. 0011: 3port (PD72870) 0001: 1port (PD72871) Indicate the maximum speed that this node supports. 010: 98.304, 196.608 and 393.216 Mbps Delay Link_active 4 1 R R/W 0010 1 Indicate worst case repeating delay time. 144+(2 x 20)=184 nsec Link active. 1: Enable 0: Disable The logical AND status of this bit and LPS. State will be referred to "L bit" of Self-ID Packet#0. 5 The LPS is a PHY/Link interface signal and is defined in P1394a draft 2.0. It is an internal signal in the PD72870,72871. Contender 1 R/W See Description Contender. "1" indicate this node support bus manager function. This bit will be referred to "C bit" of Self-ID Packet#0. The reset data is depending on CMC pin setting. CMC pin condition 1: Pull up (Contender) 0: Pull down (Non Contender) Jitter Pwr_class 3 3 R R/W 010 See Description The difference of repeating time (Max.-Min.). (2+1) x 20=60 nsec Power class. Please refer to IEEE1394 -1995 [4.3.4.1]. This bit will be referred to Pwr field of Self-ID Packet#0. The reset data will be determined by PC0-PC2 Pin status. Resume_int 1 R/W 0 Resume interrupt enable. When set to 1, if any one port does resume, the Port_event bit becomes 1. ISBR 1 R/W 0 Initiate short (arbitrated) bus reset. Setting to 1 acquires the bus and begins short bus reset. Short bus reset signal output : 1.3 sec Returns to 0 at the beginning of the bus reset. Loop 1 R/W 0 Loop detection output. 1: Detection Writing 1 to this bit clears it to 0. Writing 0 has no effect. Pwr_fail 1 R/W 0 Power cable disconnect detect. It becomes 1 when there is a change from 1 to 0 in the CPS bit. Writing 1 to this bit clears it to 0. Writing 0 has no effect. Timeout 1 R/W 0 Arbitration state machine time-out. Writing 1 to this bit clears it to 0. Writing 0 has no effect. Preliminary Data Sheet S13925EJ2V0DS00 19 PD72870,72871 Table 2-1. Bit Field Description (3/3) Field Port_event Size 1 R/W R/W Reset value 0 Description Set to 1 when the Int_Enable bit in the register map of each port is 1 and there is a change in the ports connected, Bias, Disabled and Fault bits. Set to 1 when the Resume_int bit is 1 and any one port does resume. Writing 1 to this bit clears it to 0. Writing 0 has no effect. Enab_accel 1 R/W 0 Enables arbitration acceleration. Ack-acceleration and Fly-by arbitration are enabled. 1: Enabled 0: Disabled If this bit changes while the bus request is pending, the operation is not guaranteed. Enab_multi 1 R/W 0 Enable multi-speed packet concatenation. Setting this bit to 1 follows multi-speed transmission. When this bit is set to 0,the packet will be transmitted with the same speed as the first packet. Page_select 3 R/W 000 Select page address between 1000 to 1111. 000: Port Status Page 001: Vendor Definition Page Others: Unused Port_select 4 R/W 0000 Port Selection. Selecting 000 (Port Status Page) with the page selection selects the port. PD72870 0000: Port 0 0001: Port 1 0010: Port 2 Others: Unused Reserved R 000... Reserved. Read as 0. PD72871 0000: Port 0 Others: Unused 20 Preliminary Data Sheet S13925EJ2V0DS00 PD72870,72871 2.2 Port Status Page (Page 000) Figure 2-2. Port Status Page 0 1000 1001 1010 1011 1100 1101 1110 1111 AStat Negotiated_speed 1 2 BStat Int_enable 3 4 Child Fault 5 Connected 6 Bias Reserved 7 Disabled Reserved Reserved Reserved Reserved Reserved Reserved Table 2-2. Bit Field Description Field AStat Size 2 R/W R Reset value XX A port status value. 00:---, 10: "0" 01: "1", 11: "Z" BStat 2 R XX B port status value. 00:---, 10: "0" 01: "1", 11: "Z" Child 1 R Child node status value. 1: Connected to child node 0 : Connected to parent node Connected 1 R 0 Connection status value. 1: Connected 0: Disconnected Bias 1 R Bias voltage status value. 1: Bias voltage 0: No bias voltage Disabled 1 R/W See Description Negotiated_ Speed 3 R The reset value is set by the PORTDIS pin. 1: Disable Shows the maximum data transfer rate of the node connected to this port. 000: 100 Mbps 001: 200 Mbps 010: 400 Mbps Int_enable 1 R/W 0 The Port_event is set to 1 by a change to 1 of the Connected, Bias, Disable, and Fault bits. Fault 1 R/W 0 Set to 1 if an error occurs during Suspend/Resume. Writing 1 to this bit clears it to 0. Writing 0 has no effect. Reserved R 000... Reserved. Read as 0. Description Preliminary Data Sheet S13925EJ2V0DS00 21 PD72870,72871 2.3 Vendor ID Page (Page 001) Figure 2-3. Vendor ID Page 0 1000 1001 1010 1011 1100 1101 1110 1111 Product_ID Vendor_ID 1 2 3 4 5 6 7 Compliance_level Reserved Table 2-3. Bit Field Description Field Compliance_level Vendor_ID Product_ID Reserved Size 8 24 24 R/W R R R R 000... Reset value 00000001 00004CH According to IEEE P1394a. Company ID Code value, NEC IEEE OUI. Product code. Reserved. Read as 0. Description 22 Preliminary Data Sheet S13925EJ2V0DS00 PD72870,72871 3. CONFIGURATION REGISTERS 3.1 PCI Bus Mode Configuration Register ( CARD_ON=Low ) 31 24 23 16 15 08 07 00 00H 04H Revision ID Latency Timer Base Address 0 Base Address 1 Base Address 2 Base Address 3 Base Address 4 Base Address 5 CardBus CIS Pointer Subsystem ID Subsystem Vendor ID Expansion Rom Base Address Register 000000H 00000000H Max_Lat Min_Gnt Interrupt Pin PCI_OHCI_Control 00000000H 00000000H 00000000H Diagnostic register0 Diagnostic register1 Diagnostic register2 Diagnostic register3 Power Management Capabilities Data PMCSR_BSE 00000000H 00000000H User Area (GENERAL_RegisterA) User Area (GENERAL_RegisterB) User Area (GENERAL_RegisterC) User Area (GENERAL_RegisterD) 00000000H Next_Item_Ptr Cap_ID Interrupt Line Cap_Ptr Cache Line Size 08H 0CH 10H 14H 18H 1CH 20H 24H 28H 2CH 30H 34H 38H 3CH 40H 44H 48H 4CH 50H 54H 58H 5CH 60H 64H 68H 6CH 70H 74H 78H 7CH 80H FCH Device ID Status Class Code BIST Header Type Vendor ID Command Power Management Control/Status Preliminary Data Sheet S13925EJ2V0DS00 23 PD72870,72871 3.1.1 Offset_00 Vendor ID Register This register identifies the manufacturer of the PD72870, 72871. The ID is assigned by the PCI_SIG committee. Bits 15-0 R/W R Constant value of 1033H. Description 3.1.2 Offset_02 DeviceID Register This register identifies the type of the device for the PD72870, 72871. The ID is assigned by NEC Corporation. Bits R/W R Constant value of 00CDH (PD72870 ). Constant value of 00CEH (PD72871). Description 5 15-0 3.1.3 Offset_04 Command Register The register provides control over the device's ability to generate and respond to PCI cycles. Bits 0 R/W R Description I/O enable Constant value of 0. The PD72870, 72871 does not respond to PCI I/O accesses. 1 R/W Memory enable Default value of 1. It defines if the PD72870, 72871 responds to PCI memory accesses. This bit should be set to one upon power-up reset. 0: The PD72870, 72871 does not respond to PCI memory cycles 1: The PD72870, 72871 responds to PCI memory cycles 2 R/W Master enable Default value of 1. It enables the PD72870, 72871 as bus-master on the PCI-bus. 0: The PD72870, 72871 cannot generate PCI accesses by being a bus-master 1: The PD72870, 72871 is capable of acting as a bus-master 3 R Special cycle monitor enable Constant value of 0. The special cycle monitor is always disabled. 4 R/W Memory write and invalidate enable Default value of 0. It enables Memory Write and Invalid Command generation. 0: Memory write must be used 1: The PD72870, 72871, when acts as PCI master, can generate the command 5 R VGA color palette invalidate enable Constant value of 0. VGA color palette invalidate is always disabled. 6 R/W Parity error response Default value of 0. It defines if the PD72870, 72871 responds to PERR. 0: Ignore parity error 1: Respond to parity error 7 8 R R/W Stepping enable Constant value of 0. Stepping is always disabled. System error enable Default value of 0. It defines if the PD72870, 72871 responds to SERR. 0: Disable system error checking 1: Enable system error checking 9 R Fast back-to-back enable Constant value of 0. Fast back-to-back transactions are only allowed to the same agent. 15-10 R Reserved Constant value of 000000. 24 Preliminary Data Sheet S13925EJ2V0DS00 PD72870,72871 3.1.4 Offset_06 Status Register This register tracks the status information of PCI-bus related events which are relevant to the PD72870, 72871. "Read" and "Write" are handled somewhat differently. Bits 3-0 4 6,5 7 R/W R R R R Reserved Constant value of 0000. New capabilities Constant value of 1. It indicates the existence of the Capabilities List. Description Reserved Constant value of 00. Fast back-to-back capable Constant value of 1. It indicates that the PD72870, 72871, as a target, cannot accept fast back-to-back transactions when the transactions are not to the same agent. 8 R/W Signaled parity error Default value of 0. It indicates the occurrence of any "Data Parity". 0: No parity detected (default) 1: Parity detected 10,9 R DEVSEL timing Constant value of 01. These bits define the decode timing for DEVSEL. 0: Fast (1 cycles) 1: Medium (2 cycles) 2: Slow (3 cycles) 3: undefined 11 R/W Signaled target abort Default value of 0. This bit is set by a target device whenever it terminates a transaction with "Target Abort". 0: The PD72870, 72871 did not terminate a transaction with Target Abort 1: The PD72870, 72871 has terminated a transaction with Target Abort 12 R/W Received target abort Default value of 0. This bit is set by a master device whenever its transaction is terminated with a "Target Abort". 0: The PD72870, 72871 has not received a Target Abort 1: The PD72870, 72871 has received a Target Abort from a bus-master 13 R/W Received master abort Default value of 0. This bit is set by a master device whenever its transaction is terminated with "Master Abort". The PD72870, 72871 asserts "Master Abort" when a transaction response exceeds the time allocated in the latency timer field. 0: Transaction was not terminated with a Master Abort 1: Transaction has been terminated with a Master Abort 14 R/W Signaled system error Default value of 0. It indicates that the assertion of SERR by the PD72870, 72871. 0: System error was not signaled 1: System error was signaled 15 R/W Received parity error Default value of 0. It indicates the occurrence of any PERR. 0: No parity error was detected 1: Parity error was detected Preliminary Data Sheet S13925EJ2V0DS00 25 PD72870,72871 3.1.5 Offset_08 Revision ID Register This register specifies a revision number assigned by NEC Corporation for the PD72870, 72871. Bits 7-0 R/W R Description Default value of 01H. It specifies the silicon revision. It will be incremented for subsequent silicon revisions. 3.1.6 Offset_09 Class Code Register This register identifies the class code, sub-class code, and programming interface of the PD72870, 72871. Bits 7-0 15-8 23-16 R/W R R R Description Constant value of 10H. It specifies an IEEE1394 OpenHCI-compliant Host Controller. Constant value of 00H. It specifies an "IEEE1394" type. Constant value of 0CH. It specifies a "Serial Bus Controller". 3.1.7 Offset_0C Cache Line Size Register This register specifies the system cache line size, which is PC-host system dependent, in units of 32-bit words. The following cache line sizes are supported: 2, 4, 8, 16, 32, 64, and 128. All other values will be recognized as 0, i.e. cache disabled. Bits 7-0 R/W R/W Default value of 00H. Description 3.1.8 Offset_0D Latency Timer Register This register defines the maximum amount of time that the PD72870, 72871 is permitted to retain ownership of the bus after it has acquired bus ownership and initiated a subsequent transaction. Bits 7-0 R/W R/W Description Default value of 00H. It specifies the number of PCI-bus clocks that the PD72870, 72871 may hold the PCI bus as a bus-master. 3.1.9 Offset_0E Bits 7-0 Header Type Register R/W R Description Constant value of 00H. It specifies a single function device. 3.1.10 Offset_0F BIST Register Bits 7-0 R/W R Description Constant value of 00H. It specifies whether the device is capable of Built-in Self Test. 26 Preliminary Data Sheet S13925EJ2V0DS00 PD72870,72871 3.1.11 Offset_10 Base Address 0 Register This register specifies the base memory address for accessing all the "Operation registers" (i.e. control, configuration, and status registers) of the PD72870, 72871, while the BIOS is expected to set this value during power-up reset. Bits 11-0 31-12 R/W R R/W Description Constant value of 000H. These bits are "read-only". - 3.1.12 Offset_20 Subsystem Vendor ID Register While the ID is This register identifies the subsystem that contains the NEC's PD72870, 72871 function. power-up reset. Access to this register through PCI-bus is prohibited. Bits 15-0 R/W R Default value of 1033H. Description assigned by the PCI_SIG committee, the value should be loaded into the register from the external serial ROM after 3.1.13 Offset_22 Subsystem ID Register This register identifies the type of the subsystem that contains the NEC's PD72870, 72871 function. While the ID is assigned by the manufacturer, the value should be loaded into the register from the external serial EEPROM after power-up reset. Access to this register through PCI-bus is prohibited. Bits 15-0 R/W R Default value of 0063H. Description 3.1.14 Offset_30 Expansion Rom Base Address Register This register is not supported by the current implementation of the PD72870, 72871. Bits 31-0 R/W R Reserved Constant value of 0. Description 3.1.15 Offset_34 Cap_Ptr Register This register points to a linked list of additional capabilities specific to the PD72870, 72871, the NEC's implementation of the 1394 OpenHCI specification. Bits 7-0 R/W R Description Constant value of 60H. The value represents an offset into the PD72870, 72871's PCI Configuration Space for the location of the first item in the New Capabilities Linked List. Preliminary Data Sheet S13925EJ2V0DS00 27 PD72870,72871 3.1.16 Offset_3C Interrupt Line Register This register provides the interrupt line routing information specific to the PD72870, 72871, the NEC's implementation of the 1394 OpenHCI specification. Bits 7-0 R/W R/W Description Default value of 00H. It specifies which input of the host system interrupt controller the interrupt pin of the PD72870, 72871 is connected to. 3.1.17 Offset_3D Interrupt Pin Register This register provides the interrupt line routing information specific to the PD72870, 72871, the NEC's implementation of the 1394 OpenHCI specification. Bits 7-0 R/W R Description Constant value of 01H. It specifies PCI INTA is used for interrupting the host system. 3.1.18 Offset_3E Min_Grant Register This register specifies how long of a burst period the PD72870, 72871 needs, assuming a clock rate of 33MHz. Resolution is in units of 1/4 s. The value should be loaded into the register from the external serial EEPROM upon power-up reset, and access to this register through PCI-bus is prohibited. Bits 7-0 R/W R Description Default value of 00H. Its value contributes to the desired setting for Latency Timer value. 3.1.19 Offset_3F Max Lat Register This register specifies how often the PD72870, 72871 needs to gain access to the PCI-bus, assuming a clock rate of 33MHz. Resolution is in units of 1/4 s. The value should be loaded into the register from the external serial EEPROM after hardware reset, and access to this register through PCI-bus is prohibited. Bits 7-0 R/W R Description Default value of 00H. Its value contributes to the desired setting for Latency Timer value. 3.1.20 Offset_40 PCI_OHCI_Control Register This register specifies the control bits that are IEEE1394 OpenHCI specific. Vendor options are not allowed in this register. It is reserved for OpenHCI use only. Bits 0 R/W R/W Description PCI global SWAP Default value of 0. When this bit is 1, all quadrates read from and written to the PCI Interface are byte swapped, thus a "PCI Global Swap". PCI addresses for expansion ROM and PCI Configuration registers, are, however, unaffected by this bit. This bit is not required for motherboard implementations. 31-1 R Reserved Constant value of all 0. 28 Preliminary Data Sheet S13925EJ2V0DS00 PD72870,72871 3.1.21 Offset_60 Cap_ID & Next_Item_Ptr Register The Cap_ID signals that this item in the Linked List is the registers defined for PCI Power Management, while the Next_Item_Ptr describes the location of the next item in the PD72870, 72871's Capability List. Bits 7-0 R/W R Description Cap_ID Constant value of 01H. The default value identified the Link List item as being the PCI Power Management registers, while the ID value is assigned by the PCI SIG. 15-8 R Next_Item_Ptr Constant value of 00H. It indicated that there are no more items in the Link List. 3.1.22 Offset_62 Power Management Capabilities Register This is a 16-bit read-only register that provides information on the power management capabilities of the PD72870, 72871. Bits 2-0 R/W R Description version Constant value of 001. The power management registers are implemented as defined in revision 1.0 of PCI Bus Power Management Interface Specification. 3 4 5 8,6 9 R R R R R PME clock Constant value of 0. Auxiliary power source Constant value of 0. The alternative power source is not supported. DIS Constant value of 0. Reserved Constant value of 000. D1_support Constant value of 0. The PD72870, 72871 does not support the D1 Power Management state. 10 R D2_support Constant value of 1. The PD72870, 72871 supports the D2 Power Management state. 15-11 R PME_support Constant value of 01100. Preliminary Data Sheet S13925EJ2V0DS00 29 PD72870,72871 3.1.23 Offset_64 Power Management Control/Status Register This is a 16-bit read-only register that provides control status information of the PD72870, 72871. Bits 1,0 R/W R/W Description PowerState Default value is undefined. This field is used both to determine the current power state of the PD72870, 72871 and to set the PD72870, 72871 into a new power state. As D1 is not supported in the current implementation of the PD72870, 72871, writing of `01' will be ignored. 00: D0 (DMA contexts: ON, Link Layer: ON) 01: Reserved (D1 state not supported) 10: D2 (DMA contexts: OFF, Link Layer: OFF, LPS: OFF, PME will be asserted upon LinkON being active) 11: D3 (DMA contexts: OFF, Link Layer: OFF, LPS: OFF, PME will be asserted upon LinkON being active, Power can be removed) 5 The LPS is a PHY/Link interface signal and is defined in P1394a draft 2.0. It is an internal signal in the PD72870,72871. 7-2 8 R R/W Reserved Constant value of 000000. PME_En Default value of 0. This field is used to enable the specific power management features of the PD72870, 72871. 12-9 14,13 15 R R R/W Data_Select Constant value of 0000. Data_Scale Constant value of 00. PME_Status Default value is undefined. A write of `1' clears this bit, while a write of `0' is ignored. 30 Preliminary Data Sheet S13925EJ2V0DS00 PD72870,72871 3.2 CardBus Mode Configuration Register ( CARD_ON=High ) 31 24 23 16 15 08 07 00 00H 04H Revision ID Latency Timer Base Address 0 Base Address 1 (CardBus Status Reg) Note Base Address 2 (CardBus Status Reg) Base Address 3 Base Address 4 Base Address 5 CardBus CIS Pointer Note Subsystem ID Subsystem Vendor ID Expansion Rom Base Address Register 000000H 00000000H Max_Lat Min_Gnt Interrupt Pin PCI_OHCI_Control 00000000H 00000000H 00000000H Diagnostic register0 Diagnostic register1 Diagnostic register2 Diagnostic register3 Power Management Capabilities Data PMCSR_BSE 00000000H 00000000H User Area (GENERAL_RegisterA) User Area (GENERAL_RegisterB) User Area (GENERAL_RegisterC) User Area (GENERAL_RegisterD) CIS Area Note Next_Item_Ptr Cap_ID Interrupt Line Cap_Ptr Note Device ID Status Class Code BIST Header Type Vendor ID Command 08H 0CH 10H 14H 18H 1CH 20H 24H 28H 2CH 30H 34H 38H 3CH 40H 44H 48H 4CH 50H 54H 58H 5CH 60H 64H 68H 6CH 70H 74H 78H 7CH 80H FCH Cache Line Size Power Management Control/Status Note Different from PCI Bus Mode Configuration Register. Preliminary Data Sheet S13925EJ2V0DS00 31 PD72870,72871 3.2.1 Offset_14/18 Bits 7-0 31-8 Base_Address_1/2 Register (CardBus Status Registers) R/W R R/W Constant value of 00. Description (1) Function Event Register (FER) ( Base Address 1 ( 2 )+ 0H ) Bits 0 R/W R Write Protect (No Use). Read only as `0' 1 R Ready Status (No Use). Read only as `0' 2 R Battery Voltage Detect 2 (No Use). Read only as `0' 3 R Battery Voltage Detect 1 (No Use). Read only as `0' 4 14-5 15 31-16 R/W R R/W R General Wakeup Reserved. Read only as `0' Interrupt Reserved. Read only as `0' Description (2) Function Event Mask Register (FEMR) ( Base Address 1 ( 2 )+ 4H ) Bits 0 R/W R Write Protect (No Use). Read only as `0' 1 R Ready Status (No Use). Read only as `0' 2 R Battery Voltage Detect 2 (No Use). Read only as `0' 3 R Battery Voltage Detect 1 (No Use). Read only as `0' 4 5 6 13-7 14 15 31-16 R/W R R R R/W R/W R General Wakeup Mask BAM. Read only as `0' PWM. Read only as `0' Reserved. Read only as `0' Wakeup Mask Interrupt Reserved. Read only as `0' Description 32 Preliminary Data Sheet S13925EJ2V0DS00 PD72870,72871 (3) Function Reset Status Register (FRSR) ( Base Address 1 ( 2 )+ 8H ) Bits 0 R/W R Write Protect (No Use). Read only as `0' 1 R Ready Status (No Use). Read only as `0' 2 R Battery Voltage Detect 2 (No Use). Read only as `0' 3 R Battery Voltage Detect 1 (No Use). Read only as `0' 4 14-5 15 31-16 R/W R R/W R General Wakeup Mask Reserved. Read only as `0' Interrupt Reserved. Read only as `0' Description (4) Function Force Event Register (FFER) ( Base Address 1 ( 2 )+ CH ) Bits 0 R/W R Write Protect (No Use). Read only as `0' 1 R Ready Status (No Use). Read only as `0' 2 R Battery Voltage Detect 2 (No Use). Read only as `0' 3 R Battery Voltage Detect 1 (No Use). Read only as `0' 4 14-5 15 31-16 R/W R/W R General Wakeup Mask No Use Interrupt Reserved. Read only as `0' Description 3.2.2 Offset_28 Cardbus CIS Pointer This register specifies start memory address of the Cardbus CIS Area. Bits 31-0 R/W R Starting Pointer of CIS Area. Constant value of 00000080H. Description 3.2.3 Offset_80 CIS Area The PD72870, 72871 supports external Serial ROM(AT24C02 compatible) interface. CIS Area Register can be loaded from external Serial ROM in the CIS area when CARD_ON are HIGH. CARD_ON 0 0 1 CIS_ON 1 0 X Bus PCI PCI Cardbus CIS OFF ON ON FUNCTION PME CSTSCHG CSTSCHG Preliminary Data Sheet S13925EJ2V0DS00 33 PD72870,72871 4. PHY FUNCTION 4.1 Cable Interface 4.1.1 Connections Figure 4-1. Cable Interface Connection Detection Current Connection Detection Comparator Common Mode Speed Current driver + Driver TpBias TpAp 7 k 7 k TpAn 56 56 56 56 TpBp 7 k 7 k TpBn Receiver + Arbitration Comparators + + Common Mode Comparator + Connection Detection Current Connection Detection Comparator Driver Receiver + Arbitration Comparators + + Common Mode Comparators + + - 1 F 0.01 F 5.1 k 270 pF Common Mode Speed Current Driver TpBias TpBp Driver 7 k 7 k TpBn Receiver + Arbitration Comparators + + Common Mode Comparator + 270 pF 5.1 k 0.01 F 1 F 56 56 56 56 TpAp 7 k 7 k TpAn + Driver Receiver + Arbitration Comparators + + Common Mode Comparators + + - 34 Preliminary Data Sheet S13925EJ2V0DS00 PD72870,72871 4.1.2 Cable Interface Circuit Each port is configured with two twisted-pairs of TpA and TpB. TpA and TpB are used to monitor the state of the Transmit/Receive line, control signals, data and cables. During transmission to the IEEE1394 bus, the Data/Strobe signal received from the Link layer controller is encoded, converted from parallel to serial and transmitted. While receiving from the IEEE1394 bus, the Data/Strobe signal from TpA, TpB is converted from serial to parallel after synchronization by SCLK Note, then transmitted to the Link layer controller in 2/4/8 bits according to the data rate of 100/200/400 Mbps. The bus arbitration for TpA and TpB and the state of the line are monitored by the built-in comparator. The state of the 1394 bus is transmitted to the state machine in the LSI. 5 Note The SCLK is a PHY/Link interface signal and is defined in P1394a draft 2.0. It is an internal signal in the PD72870,72871. 4.1.3 CPS An external resistance of 390 k is connected in series to the power cable to monitor the power of the power cable. If the cable power falls under 7.5 V there is an indication to the Link layer that the power has failed. 4.1.4 Unused Ports TpAp, TpAn : Not connected TpBp, TpBn : AGND TpBias : Connected to AGND using a 1.0 F load capacitor 4.2 PLL and Crystal Oscillation Circuit 4.2.1 Crystal Oscillation Circuit To supply the clock of 24.576 MHz 100 ppm, use an external capacitor of 10 pF and a crystal of 50 ppm. 4.2.2 PLL The crystal oscillator multiplies the 24.576 MHz frequency by 16 (393.216 MHz). 4.3 PC0-PC2, CMC CMC shows the bus manager function which corresponds to the c bit of the Self_ID packet and the Contender bit in the PHY register when the input is High. The value of CMC can be changed with software through the Link layer; this pin sets the initial value during Poweron Reset. Use a pull-up or pull-down resistor of 10 k, based on the device's specification. The PC0-PC2 pin corresponds to the power field of the Self_ID packet and Pwr_class in the PHY register. Refer to Section 4.3.4.1 of the IEEE1394-1995 specification for information regarding the Pwr_class. The value of Pwr can be changed with software through the Link layer; this pin sets the initial value during Power-on Reset. Use a pull-up or pull-down resistor of 10 k based on the application. 4.4 P_RESETB Connect an external capacitor of 0.1 F between the pins P_RESETB and GND. If the voltage drops below 0 V, a reset pulse is generated. All of the circuits are initialized, including the contents of the PHY register. 4.5 RI0, RI1 Connect an external resistor of 9.1 k to limit the LSI's current. Preliminary Data Sheet S13925EJ2V0DS00 35 PD72870,72871 5. SERIAL ROM INTERFACE The PD72870, 72871 provides a serial ROM interface to initialize the 1394 Global Unique ID Register and the PCI/Cardbus Mode Configuration registers from a serial EEPROM. 5 5.1 Serial EEPROM Register Register Address Base address + 0x930 Base address + 0x934 Base address + 0x938 Base address + 0x93C Base address + 0x940 Base address + 0x95C Base address + 0x960 Base address + 0x984 SUBID register LATVAL register W_GUIDHi register W_GUIDLo register Parameters Write register W_GENERAL register W_PHYS register W_CIS register Register Name R/W R/W R/W R/W R/W R/W R/W R/W R/W Remark Base address : Base Address 0 in Configuration register 5 5.2 Serial EEPROM Register Description (1) SUBID register (Base address + 0x930) 31 W_SUBSYSID 16 15 W_SUBVNDID 0 Field W_SUBSYSID Bits 31-16 R/W R/W Default value 0063H Description Subsystem ID value. The value is loaded into Subsystem ID register in Configuration register (offset+2CH bit 31-16). W_SUBVNDID 15-0 R/W 1033H Subsystem Vendor ID value. The value is loaded into Subsystem Vendor ID register in Configuration register (Offset+2CH bit 15-0). (2) LATVAL register (Base address + 0x934) 31 W_MAXLAT 24 23 W_MINGNT 16 15 -012 11 10 1 -04 3 0 W_MAX_REC Field W_MAXLAT Bits 31-24 R/W R/W Default value 00H Description Max Latency value. The value is loaded into Max Latency register in Configuration register (Offset+3CH bit 31-24). W_MINGNT 23-16 R/W 00H Min Grant value. The value is loaded into Min Grant register in Configuration register (Offset+3CH bit 23-16). - 15-12 11 10-4 R/W 9H Reserved. Write 0 to these bits. Reserved. Write 1 to this bit. Reserved. Write 0 to these bits. MAX__REC value. The value is loaded into the max_rec field of OHCI BusOption register in OHCI register (Offset+020H bit 15-12). W_MAX_REC 3-0 36 Preliminary Data Sheet S13925EJ2V0DS00 PD72870,72871 (3) W_GUIDHi register (Base address + 0x938) 31 W_GUIDHi 0 Field W_GUIDHi Bits 31-0 R/W R/W Default value Undefined Description GlobalUniqueIDHi value. The value is loaded into OHCI GlobalUniqueIDHi register in OHCI register (Offset+024H bit 31-0). Please refer to the 1394 Open Host Controller Interface Specification/Release 1.0 [5.5.5]. (4) W_GUIDLo register (Base address + 0x93C) 31 W_GUIDLo 0 Field W_GUIDLo Bits 31-0 R/W R/W Default value Undefined Description GlobalUniqueIDLo value. The value is loaded into GlobalUniqueIDLo register in OHCI register (Offset+028H bit 31-0). Please refer to the 1394 Open Host Controller Interface Specification/Release 1.0 [5.5.5]. (5) Parameters Write register (Base address + 0x940) 31 -07 6 4 3 -01 0 PAR _W PAGE_S Field PAGE_S Bits 31-7 6-4 R/W R/W Default value 000 Reserved. Write 0 to these bits. Description Write register select page. The bit field returns zero when read. 000: Select SUBID register and LATVAL register. 001: Select W_GUIDHi register and W_GUIDLo register. 010: Select W_GENERAL register (W_GENERAL_0 and W_GENERAL_1). 011: Select W_GENERAL register (W_GENERAL_2 and W_GENERAL_3). 100: Select W_PHYS register (W_ programPhyEnable, W_aPhyEnhanceEnable). 101: Select W_CIS register (W_CIS_EVEN - W_CIS_ODD). PAR_W 3-1 0 R/W 0 Reserved. Write 0 to these bits. Write control signal. The bit field returns zeros when read. 1: Write the value of select page defined PAGE_S. One write transaction is the units of 8 byte. 0: Ignored. Preliminary Data Sheet S13925EJ2V0DS00 37 PD72870,72871 (6) W_GENERAL register (Base address + 0x950 - 0x95C) 31 W_GENERAL_0 (Base address + 0x950) - W_GENERAL_3 (Base address + 0x95C) 0 Field W_GENERAL_0 W_GENERAL_3 Bits 31-0 R/W R/W Default value Undefined Description User define value. The value is loaded into GENERAL_registerA - D in Configuration register (Offset+70H - 7BH). (7) W_PHYS register (Base address + 0x960) 31 -010 9 8 7 -0W_aPhyEnhanceEnable W_programPhyEnable 3 2 -10 Field W_programPhyEnable Bits 31-10 9 R/W R/W Default value 1 Reserved. Write 0 to these bits. Description programPhyEnable bit. The bit is loaded into HCControl registers in OHCI register ((Offset+50H bit 23) and (54H bit 23)). Please refer to the 1394 Open Host Controller Interface Specification/Release 1.0 [5.7]. 1: P1394a enhancement is supported. 0. P1394a enhancement is not supported. W_aPhyEnhanceEnable 8 R/W 0 aPhyEnhanceEnable bit. The bit is loaded into HCControl registers in OHCI register ((Offset+50H bit 23) and (54H bit 23)). - 7-3 2-0 - - Reserved. Write 0 to these bits. Reserved. Write 1 to these bits. (8) W_CIS register (Base address + 0x980 - 0x984) 31 W_CIS_EVEN (Base address + 0x980) - W_CIS_ODD (Base address + 0x984) 0 Field W_CIS_EVEN W_CIS_ODD Bits 31-0 R/W R/W Default value Undefined Description CIS Area value. The value is loaded into CIS Area in Configuration register (Offset+80H - FCH). 38 Preliminary Data Sheet S13925EJ2V0DS00 PD72870,72871 Table 5-1. Serial EEPROM Memory Map Byte address 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 : : 1C 1D 1E 1F 20 21 22 23 : : 28 29 2A 2B : : A4 A5 A6 A7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 W_SUBSYSID(31 : 24) W_SUBSYSID(23 : 16) W_SUBVNDID(15 : 8) W_SUBVNDID( 7 : 0) W_MAXLAT(31 : 24) W_MINGNT(23 : 16) 0 0 W_GUIDHi(31 : 24) W_GUIDHi(23 : 16) W_GUIDHi(15 : 8) W_GUIDHi( 7 : 0) W_GUIDLo(31 : 24) W_GUIDLo(23 : 16) W_GUIDLo(15 : 8) W_GUIDLo( 7 : 0) W_GENERAL_0(31 : 24) W_GENERAL_0(23 : 16) W_GENERAL_0(15 : 8) W_GENERAL_0( 7 : 0) : : W_GENERAL_3(31 : 24) W_GENERAL_3(23 : 16) W_GENERAL_3(15 : 8) W_GENERAL_3( 7 : 0) 0 0 0 0 : : W_CIS_0(31 : 24) W_CIS_0(23 : 16) W_CIS_0(15 : 8) W_CIS_0( 7 : 0) : : W_CIS_31(31 : 24) W_CIS_31(23 : 16) W_CIS_31(15 : 8) W_CIS_31( 7 : 0) 0 0 0 0 0 0 0 1 0 0 WPE 1 0 0 WPEE 1 1 0 0 0 W_MAX_REC( 3 : 0) WPE: W_programPhyEnable, WPEE: W_aPhyEnhanceEnable Preliminary Data Sheet S13925EJ2V0DS00 39 PD72870,72871 5 5.3 Load Control GROM_EN CARD_ON 0 1 X 0 CIS_ON X 1 No loading. W_SUBSYSID, W_SUBVNDID, W_MAXLAT, W_MINGNT, W_MAX_REC, W_GUIDHi/Lo, W_GENERAL_0 - W_GENERAL_3, W_programPhyEnable, W_aPhyEnhanceEnable are loaded. 1 1 0 1 0 X All parameters (W_SUBSYSID, W_SUBVNDID, W_MAXLAT, W_MINGNT, W_MAX_REC, W_GUIDHi/Lo, W_GENERAL_0 - W_GENERAL_3, W_programPhyEnable, W_aPhyEnhanceEnable, W_CIS_EVEN - W_CIS_ODD) are loaded. Description 40 Preliminary Data Sheet S13925EJ2V0DS00 PD72870,72871 5 6. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Parameter Power supply voltage Input voltage Symbol VDD VI LVTTL @ (VI < 0.5 V + VDD) PCI @ (VI < 3.0 V + VDD) Output voltage VO LVTTL @ (VO < 0.5 V + VDD) PCI @ (VO < 3.0 V + VDD) Operating temperature Storage temperature TA Tstg Condition Rating -0.5 to +4.6 -0.5 to +4.6 -0.5 to +6.6 -0.5 to +4.6 -0.5 to +6.6 0 to +70 -65 to +150 Unit V V V V V C C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Ranges Parameter Power supply voltage Symbol VDD Condition Used to clamp reflection on PCI bus. Rating 4.5 to 5.5 3.0 to +3.6 Operating temperature TA 0 to +70 Unit V V C Preliminary Data Sheet S13925EJ2V0DS00 41 PD72870,72871 DC Characteristics (VDD = 3.3 V 10%, VSS = 0 V, TA= 0C to +70C) Parameter High-level input voltage Low-level input voltage High-level output current Symbol VIH VIL IOH VOH =2.4 V Pin No. LQFP:153,154 FPBGA:A4,B4 Pin No. LQFP:74,76-79,83,84,92 FPBGA:L14,P15,P16, R13-R15,T14,T15 Condition MIN. 2.0 -0.5 -6 TYP. MAX. VDD+0.5 0.8 Unit V V mA -9 mA Low-level output current IOL VOL =0.4 V Pin No. LQFP:153,154 FPBGA:A4,B4 Pin No. LQFP:74,76-79,83,84,92 FPBGA:L14,P15,P16, R13-R15,T14,T15 6 mA 9 mA Input leakage current PCI interface High-level input voltage Low-level input voltage High-level output current Low-level output current Input leakage current Cable interface Differential input voltage IL VIN = VDD or GND 10.0 A VIH VIL IOH IOL IL VOH = 2.4 V VOL = 0.4 V VIN = VDD or GND 2.0 -0.5 -2 9 5.5 0.8 V V mA mA 10.0 A VID Cable input, 100 Mbps operation Cable input, 200 Mbps operation Cable input, 400 Mbps operation 142 132 118 1.165 0.935 0.523 172.0 1.665 1.438 1.030 -0.81 -4.84 -12.40 260 260 260 2.515 2.515 2.515 265.0 2.015 2.015 2.015 0.44 -2.53 -8.10 7.5 mV mV mV V V V mV V V V mA mA mA V V TpB common mode input voltage VICM 100 Mbps speed signaling off 200 Mbps speed signaling 400 Mbps speed signaling Differential output voltage TpA common mode output voltage V0D V0CM Cable output (Test load 55) 100 Mbps speed signaling off 200 Mbps speed signaling 400 Mbps speed signaling TpA common mode output current ICM 100 Mbps speed signaling off 200 Mbps speed signaling 400 Mbps speed signaling Power status threshold voltage TpBias output voltage VTH VTPBIAS CPS 1.665 2.015 42 Preliminary Data Sheet S13925EJ2V0DS00 PD72870,72871 Remarks 1. Digital core runs at 3.3 V. 2. PCI Interface can run at 5 or 3.3 V, depending on the choice of 5 V-PCI or 3.3 V-PCI. 3. All other I/Os are 3.3 V driving, and 5 V tolerant. 4. 5 V are used only for 5 V-PCI clamping diode. 3.3 V 5.0 V Protection Circuit I/O Buffer AC Characteristics PCI Interface See PCI local bus specification Revision 2.1. Serial ROM Interface See AT24C01A/02/04/08/16 Spec. Sheet. Preliminary Data Sheet S13925EJ2V0DS00 43 PD72870,72871 5 7. APPLICATION CIRCUIT EXAMPLE 0.1F 0.1F 0.1F Note 0.1F 0.1F Note Note 33 F 0.1F Analog GND 0.1F 33 F 5.1k 270pF 5.1k 270pF 0.01 F 0.01 F 0.01 F 5.1k 270pF Analog GND Vp (Cable Supply Voltage) 1.0 F 1.0 F 1.0 F 0.1F 56 56 56 56 56 56 56 56 56 56 56 56 390 k 9.1 k (0.5%) 0.1F 0.1F 33 F Digital GND 0.1F 0.1F 0.1F 0.1F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 L _ VD D CLKRUN PME INTA PRST PCLK GNT REQ DGND P C I _ VD D AD31 AD30 AD29 AD28 DGND AD27 AD26 AD25 AD24 L _ VD D DGND CBE3 IDSEL AD23 AD22 AD21 AD20 DGND AD19 AD18 P C I _ VD D AD17 AD16 DGND CBE2 FRAME IRDY TRDY DEVSEL L _ VD D DGND IC(L) IC(L) CARD_ON CIS_ON GROM_EN GROM_SCL GROM_SDA DGND L_VDD DGND P_DVDD P_AVDD P_AVDD P_AVDD AGND AGND AGND AGND AGND TpA0p TpA0n TpB0p TpB0n TpA1p TpA1n TpB1p TpB1n TpA2p TpA2n TpB2p TpB2n TpBias0 TpBias1 TpBias2 P_AVDD AGND CPS RI1 RI0 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 P _ A VD D 1 2 0 AGND 119 XO 118 XI 1 1 7 P _ A VD D 1 1 6 FIL0 1 1 5 FIL1 1 1 4 AGND 113 AGND 112 P _ A VD D 1 1 1 P_RESETB 110 DGND 109 P _ D VD D 1 0 8 P _ A VD D 1 0 7 SUS_RESM 106 PORTDIS 105 DGND 104 P _ D VD D 1 0 3 IC(L) 1 0 2 IC(L) 1 0 1 IC(H) 1 0 0 IC(H) 9 9 DGND 98 P _ D VD D 9 7 CMC 96 PC2 95 PC1 94 PC0 93 IC(N) 9 2 IC(L) 9 1 DGND 90 IC(L) 8 9 IC(N) 8 8 IC(N) 8 7 IC(N) 8 6 DGND 85 IC(N) 8 4 IC(N) 8 3 IC(N) 8 2 L _ VD D 8 1 10 pF 0.1F 10 pF 0.1F 0.1 F 0.1 F 0.1F 0.1F 0.1F 0.1F 3 3F Digital GND 0.1F 0.1F 0.1F 0.1F 33 F Digital GND 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 0.1F 0.1F 0.1F 0.1F DGND STOP PERR SERR PAR L_VDD CBE1 DGND AD15 AD14 PCI_VDD AD13 AD12 DGND AD11 AD10 AD9 AD8 L_VDD CBE0 AD7 AD6 AD5 AD4 DGND AD3 AD2 AD1 AD0 PCI_VDD DGND L_VDD PIN_EN IC(N) IC(H) IC(N) IC(N) IC(N) IC(N) DGND Power (3.3 V) 0.1F 33 F Digital GND Note Common mode choke. Recommendation : TOKO Part No.857CM-0009 (TYPE B5W) 44 Preliminary Data Sheet S13925EJ2V0DS00 PD72870,72871 8. PACKAGE DRAWINGS 160-PIN PLASTIC LQFP (FINE PITCH) (24x24) A B 120 121 81 80 detail of lead end S C D R Q 160 1 41 0 4 F G H I M J P K S N S L M NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 26.00.2 24.00.2 24.00.2 26.00.2 2.25 2.25 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.00.2 0.50.2 0.145+0.055 -0.045 0.10 1.40.1 0.1250.075 3 +7 -3 1.7 MAX. S160GM-50-8ED-3 Preliminary Data Sheet S13925EJ2V0DS00 45 PD72870,72871 192-PIN PLASTIC FBGA (14 x 14mm) 14 + 0.1 0.3 3 - 1.0 13.4 + 0.1 9.5 16 15 14 13 12 4.75 11 13.4 + 0.1 10 14 + 0.1 9 8 7 6 5 4 3 INDEX MARK 2 1 4 - C1.0 T R P N M L K B J H G F E D C B A A 1.2 4 - R0.3 MAX. 25 O 1.31 + 0.15 0.96 // 0.20 S 0.36 S 0.8 0.10 S 1.0 0.35 + 0.1 0.5 +0.05 -0.10 0.08 M S AB 46 Preliminary Data Sheet S13925EJ2V0DS00 PD72870,72871 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Preliminary Data Sheet S13925EJ2V0DS00 47 PD72870,72871 EEPROM is a trademark of NEC Corporation. The export of this product from Japan is prohibited without governmental license. To export or re-export this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. * The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8 |
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